What is the difference between the following lc 3 instructions a and b

The single-cycle datapath is not used in modern processors, because it is inefficient. The critical path longest propagation sequence through the datapath is five components for the load instruction. The cycle time t c is limited by the settling time t s of these components. Additionally, as shown in the table on p.

The result is that the Load instruction takes 5 units of time, while the Store and R-format instructions take 4 units of time.

All the other types of instructions that the datapath is designed to execute run faster, requiring three units of time. The problem of penalizing addition, subtraction, and comparison operations to accomodate loads and stores leads one to ask if multiple cycles of a much faster clock could be used for each part of the fetch-decode-execute cycle.

In practice, this technique is employed in CPU design and implementation, as discussed in the following sections on multicycle datapath design. In Section 5, we will show that datapath actions can be interleaved in time to yield a potentially fast implementation of the fetch-decode-execute cycle that is formalized in a technique called pipelining. Multicycle Datapath Design In Sections 4. In this section, we use the single-cycle datapath components to create a multi-cycle datapath, where each step in the fetch-decode-execute sequence takes one cycle.

This approach has two advantages over the single-cycle datapath: Each functional unit e. In contrast, the single-cycle datapath that we designed previously required every instruction to take one cycle, so all the instructions move at the speed of the slowest.

We next consider the basic differences between single-cycle and multi-cycle datapaths. Cursory Analysis. Observe the following differences between a single-cycle and multi-cycle datapath: In the multicycle datapath, one memory unit stores both instructions and data, whereas the single-cycle datapath requires separate instruction and data memories. The multicycle datapath uses on ALU, versus an ALU and two adders in the single-cycle datapath, because signals can be rerouted throuh the ALU in a multicycle implementation.

In the single-cycle implementation, the instruction executes in one cycle by design and the outputs of all functional units must stabilize within one cycle. In contrast, the multicycle implementation uses one or more registers to temporarily store buffer the ALU or functional unit outputs. This buffering action stores a value in a temporary register until it is needed or used in a subsequent clock cycle.

Note that there are two types of state elements e. Thus, the additional buffer registers determine a what functional units will fit into a given clock cycle and b the data required for later cycles involved in executing the current instruction.

In the simple implementation presented herein, we assume for purposes of illustration that each clock cycle can accomodate one and only one of the following operations: Memory access Register file access two reads or one write ALU operation arithmetic or logical 4.

New Registers. As a result of buffering, data produced by memory, register file, or ALU is saved for use in a subsequent cycle. The IR and MDR are distinct registers because some operations require both instruction and data in the same clock cycle. Since all registers except the IR hold data only between two adjacent clock cycles, these registers do not need a write control signal. In contrast, the IR holds an instruction until it is executed multiple clock cycles and therefor requires a write control signal to protect the instruction from being overwritten before its execution has been completed.

New Muxes. The muxes also route to one ALU the many inputs and outputs that were distributed among the several ALUs of the single-cycle datapath. Thus, we make the following additional changes to the single-cycle datapath: Add a multiplexer to the first ALU input, to choose between a the A register as input for R- and I-format instructions , or b the PC as input for branch instructions. On the second ALU, the input is selected by a four-way mux two control bits.

The two additional inputs to the mux are a the immediate constant value 4 for incrementing the PC and b the sign-extended offset, shifted two bits to preserve alighment, which is used in computing the branch target address.

The details of these muxes are shown in Figure 4. By adding a few registers buffers and muxes inexpensive widgets , we halve the number of memory units expensive hardware and eliminate two adders more expensive hardware.

New Control Signals. The datapath shown in Figure 4. As a result, it will require different control signals than the single-cycle datapath, as follows: Write Control Signals for the IR and programmer-visible state units Read Control Signal for the memory; and Control Lines for the muxes. It is advantageous that the ALU control from the single-cycle datapath can be used as-is for the multicycle datapath ALU control. However, some modifications are required to support branches and jumps.

We describe these changes as follows. Branch and Jump Instruction Support. We call the latter the branch taken condition. The implementational goal is balancing of the work performed per clock cycle, to minimize the average time per cycle across all instructions. For example, each step would contain one of the following: ALU operation Register file access two reads or one write Memory access one read or one write Thus, the cycle time will be equal to the maximum time required for any of the preceding operations.

Note : Since a the datapath is designed to be edge-triggered reference Section 4. The new value, output from ALU, register file, or memory, is not available in the register until the next clock cycle.

Multicycle datapath control signals and their functions [MK98]. In the multicycle datapath, all operations within a clock cycle occur in parallel, but successive steps within a given instruction operate sequentially.

Several implementational issues present that do not confound this view, but should be discussed. In contrast, the register file has more complex hardware as shown in Section 4.

We next examine multicycle datapath execution in terms of the fetch-decode-execute sequence. Instruction Fetch. The PC is sent via control circuitry as an address to memory.

The memory hardware performs a read operation and control hardware transfers the instruction at Memory[PC] into the IR, where it is stored until the next instruction is fetched.

Fortunately, incrementing the PC and performing the memory read are concurrent operations, since the new PC is not required at the earliest until the next clock cycle.

Reading Assigment : The exact sequence of operations is described on p. Instruction Decode and Data Fetch. Included in the multicycle datapath design is the assumption that the actual opcode to be executed is not known prior to the instruction decode step.

This is reasonable, since the new instruction is not yet available until completion of instruction fetch and has thus not been decoded. As a result of not knowing what operation the ALU is to perform in the current instruction, the datapath must execute only actions that are: Applicable to all instructions and Not harmful to any instruction.

We can thus read the operands corresponding to rs and rt from the register file. If we don't need one or both of these operands, that is not harmful. Otherwise, the register file read operation will place them in buffer registers A and B, which is also not harmful. Another action the datapath can perform is computation of the branch target address using the ALU, since this is the instruction decode step and the ALU is not yet needed for instruction execution.

If the instruction that we are decoding in this step is not a branch, then no harm is done - the BTA is stored in ALUout and nothing further happens to it. We can perform these preparatory actions because of the of MIPS instruction formats. In this cycle, we know what the instruction is, since decoding was completed in the previous cycle.

The instruction opcode determines the datapath operation, as in the single-cycle datapath. Control signals are set as described on p. The control signals are further described on p.

Salient hardware control actions are discussed on p. Memory Access or R-format Instruction Completion. From the preceding sequences as well as their discussion in the textbook, we are prepared to design a finite-state controller, as shown in the following section.

Finite State Control Reading Assignments and Exercises In the single-cycle datapath control, we designed control hardware using a set of truth tables based on control signals activated for each instruction class. However, this approach must be modified for the multicycle datapath, which has the additional dimension of time due to the stepwise execution of instructions.

Thus, the multicycle datapath control is dependent on the current step involved in executing an instruction, as well as the next step. There are two alternative techniques for implementing multicycle datapath control. First, a finite-state machine FSM or finite state control FSC predicts actions appropriate for datapath's next computational step. This prediction is based on a the status and control information specific to the datapath's current step and b actions to be performed in the next step.

A second technique, called microprogramming , uses a programmatic representation to implement control, as discussed in Section 4. Appendix C of the textbook shows how these representations are translated into hardware. The following features are important: Current state and inputs; Next-state function, also called the transition function , which converts inputs to a a new state, and b outputs of the FSM; and Outputs, which in the case of the multicycle datapath, are control signals that are asserted when the FSM is in a given state.

Implementationally, we assume that all outputs not explicitly asserted are deasserted. Additionally, all multiplexer controls are explicitly specified if and only if they pertain to the current and next states. Finite State Control The FSC is designed for the multicycle datapath by considering the five steps of instruction execution given in Section 4. Each state in the FSM will thus a occupy one cycle in time, and b store its results in a temporary buffer register.

From the discussion of Section 4. Also note that oafter completion of an instruction, the FSC returns to its initial state Step 1 to fetch another instruction, as shown in Figure 4. High-level abstract representation of finite-state machine for the multicycle datapath finite-state control.

Figure numbers refer to figures in the textbook [Pat98,MK98]. Let us begin our discussion of the FSC by expanding steps 1 and 2, where State 0 the initial state corresponds to Step 1. Instruction Fetch and Decode. The control signals asserted in each state are shown within the circle that denotes a given state. The edges lines or arrows between states are labelled with the conditions that must be fulfilled for the illustrated transition between states to occur.

Patterson and Hennessey call the process of branching to different states decoding , which depends on the instruction class after State 1 i. Representation of finite-state control for the instruction fetch and decode states of the multicycle datapath. Memory Reference. The memory reference portion of the FSC is shown in Figure 4.

Here, State 2 computes the memory address by setting ALU input muxes to pass the A register base address and sign-extended lower 16 bits of the offset shifted left two bits to the ALU. State 5: Activated if sw store word instruction is used, and MemWrite is asserted. Representation of finite-state control for the memory reference states of the multicycle datapath.

When State 5 completes, control is transferred to State 0. Otherwise, State 3 completes and the datapath must finish the load operation, which is accomplished by transferring control to State 4. The next state is State 0. R-format Execution. State 7 causes a the register file to write assert RegWrite , b rd field of the instruction to have the number of the destination register assert RegDst , and c ALUout selected as having the value that must be written back to the register file as the result of the ALU operation by deasserting MemtoReg.

Representation of finite-state control for the R-format instruction execution states of the multicycle datapath. Branch Control. Since branches complete during Step 3, only one new state is needed. Representation of finite-state control for a branch and b jump instruction-specific states of the multicycle datapath. Jump Instruction. Similar to branch, the jump instruction requires only one state 9 to complete execution. The value written to the PC is the lower 26 bits of the IR with the upper four bits of PC, and the lower two bits equal to 00 2.

When computing the performance of the multicycle datapath, we use this FSM representation to determine the critical path maximum number of states encountered for each instruction type, with the following results: Load: 5 states Store: 4 states R-format ALU instructions: 4 states Branch: 3 states Jump: 3 states Since each state corresponds to a clock cycle according to the design assumption of the FSC controller in Section 4.

Reading Assigment : Know in detail the example computation of CPI for the multicycle datapath, beginning on p. The textbook example shows CPI for the gcc benchmark is 4. Combinatorial logic implements the transition function and a state register stores the current state of the machine e.

The inputs are the IR opcode bits, and the outputs are the various datapath control signals e. We next consider how the preceding function can be implemented using the technique of microprogramming. Microprogrammed Control Reading Assignments and Exercises While the finite state control for the multicycle datapath was relatively easy to design, the graphical approach shown in Section 4.

Recall that the FSC of Section 4. A control system for a realistic instruction set even if it is RISC would have hundreds or thousands of states, which could not be represented conveniently using the graphical technique of Section 4. However, it is possible to develop a convenient technique of control system design and programming by using abstractions from programming language practice.

This technique, called microprogramming , helps make control design more tractable and also helps improve correctness if good software engineering practice is followed.

By using very low-level instructions called microinstructions that set the value of datapath control signals, one can write microprograms that implement a processor's control system s. To do this, one specifies: Microinstruction Format that formalizes the structure and content of the microinstruction fields and functionality; Sequencing Mechanism , which determines whether the next instruction, or one indicated by a branch control structure, will be executed; and Exception Handling that determines what actions control should take when an error occurs e.

We consider these issues, as follows. Microinstruction Format A microinstruction is an abstraction of low-level control that is used to program control logic hardware.

The microinstruction format should be simple, and should discourage or prohibit inconsistency. An inconsistent microinstruction requires a given control signal to be set to two different values simultaneously, which is physically impossible. The implementation of each microinstruction should, therefore, make each field specify a set of nonoverlapping values. Signals that are never asserted concurrently can thus share the same field. The first six fields control the datapath, while the last field controls the microinstruction sequencing deciding which microinstruction will be executed next.

Memory Specify read or write, and the source for a write. For a read, specify the destination register. The microinstructions are usually referenced by sequential addreses to simplify sequencing. The sequencing process can have one of the following three modes: Incrementation , by which the address of the current microinstruction is incremented to obtain the address of the next microinstruction.

Thsi is indicated by the value Seq in the Sequencing field of Table 4. Branching , to the microinstruction that initiates execution of the next MIPS instruction.

This is implemented by the value Fetch in the Sequencing field. Control-directed choice , where the next microinstruction is chosen based on control input. We call this operation a dispatch.

This is implemented by one or more address tables similar to a jump table called displatch tables. The hardware implementation of dispatch tables is discussed in Section C.

In the current subset of MIPS whose multicycle datapath we have been implementing, we need two dispatch tables, one each for State 1 and State 2. The use of a dispatch table numbered i is indicated in the microinstruction by putting Dispatch i in the Sequencing field. Field Name Values for Field Field Functionality Label Any string Labels control sequencing, per p. Detected inconsistencies are flagged and must be corrected prior to hardware implementation. Microprogramming the Datapath Control In this section, we use the fetch-decode-execute sequence that we developed for the multicycle datapath to design the microprogrammed control.

First, we observe that sometimes an instruction might have a blank field. This is permitted when: A field that controls a functional unit e.

A field that only specifies control of an input multiplexer for a functional unit, when left blank, implies that the datapath does not care about what value the output of the mux has. We can now create the microprogram in stepwise fashion. Instruction Fetch and Decode, Data Fetch. Each instruction execution first fetches the instruction, decodes it, and computes both the sequential PC and branch target PC if applicable.

The memory field reads the instruction at address equal to PC, and stores the instruction in the IR. Register control causes data referenced by the rs and rt fields to be placed in ALU input registers A and B.

Dispatch Tables. Patterson and Hennessey consider the dispatch table as a case statement that uses the opcode field and dispatch table i to select one of N i different labels. Each of these labels points to a different microinstruction sequence that can be thought of as a kind of subprogram.

Each microcode sequence can be thought of as comprising a small utility that implements the desired capability of specifying hardware control signals. Memory Reference Instructions. Branch and Jump Execution. Observe that these ten instructions correspond directly to the ten states of the finite-state control developed in Section 4.

In more complex machines, microprogram control can comprise tens or hundreds of thousands of microinstructions, with special-purpose registers used to store intermediate data. Implementing a Microprogram It is useful to think of a microprogram as a textual representation of a finite-state machine.

Thus, a microprogram could be implemented similar to the FSC that we developed in Section 4. However, it is often useful to store the control function in a ROM, then implementing the sequencing function in some other way. Typically, the sequencer uses an incrementer to choose the next control instruction. Here, the microcode storage determines the values of datapath control lines and the technique of selecting the next state. Address select logic contains dispatch tables in ROMs or PLAs and determines the next microinstruction to execute, albeit under control of the address select outputs.

This technique is preferred, since it substitutes a simple counter for more complex address control logic, which is especially efficient if the microinstructions have little branching. Using a ROM, the microcode can be stored in its own memory and is addressed by the microprogram counter, similar to regular program instructions being addressed by an instruction sequencer. Hey moon lit do u still have the answers to those questions.

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Share More sharing options Followers 0. Recommended Posts. Posted November 8, Fill in the two missing instructions so that the four instruction sequence will do the job: 1 : 2 : 3 : 4 : 3 The PC contains x What is it?

Replace the store indirect instruction in the code below with whatever instructions are necessary to perform the same function: x x x x x Link to comment Share on other sites More sharing options Posted November 10, Posted November 13, It's ok I've got some answers figured out. Thanks anyway. Posted December 11,